There are many techniques for forming a chip carrier structure on which an integrated circuit (I/C) chip is attached, and which carrier in turn is attached to a PC board or card. In one technique known as wire bonding, an I/C chip having a plurality of wire leads extending therefrom has these leads bonded to lead wire bond pads formed on one surface of a substrate of a dielectric material which forms a chip carrier. Following the bonding process, a plastic encapsulating material, such as Hysol 4450 or Hysol 4451 sold by Hysol Corp. which are epoxy resins, is applied as a viscous fluid which cures and encapsulates the chip, the lead wires and the wire bond pads so as to protect the chip and its attachment both from exposure to the atmosphere and to any unwanted mechanical contacts. This carrier is then attached to a circuit board or card to form a populated circuit board or card structure.
One conventional way of attaching the chip carrier substrate to the circuit board or card is by means of solder ball connections in which ball grid array (BGA) pads are provided on the carrier which are connected by subsurface wiring on the chip carrier to the wire bond pads, with the BGA pads being connected by the solder balls to corresponding pads on the circuit board or circuit card. These BGA pads may be formed on the same side as the wire bond pads to which the wires of the chip are attached, or they may be formed on the opposite side. If they are formed on the opposite side from that on which the wire bond pads are located and to which the I/C chip is attached and there are no other electrical connections on the same surface as the wire bond pads for the I/C chip, then the step of applying the plastic encapsulant to the chip, the wires and the wire bond pads does not have close tolerances as to how much spread of the encapsulant can be tolerated on the surface of the chip carrier substrate. However, if the BGA pads or other electrical connections are in relatively close proximity to the wire bond pads on the same side of the chip carrier substrate, then the control of the spread of the encapsulant for encapsulating the chip, the wires and the wire bond pads becomes quite critical. On the one hand, it is necessary that sufficient encapsulant be applied to completely cover not only the chip and the wires thereon, but also the wire bond pads on the surface of the chip carrier substrate, providing the necessary protection as indicated above. On the other hand, it is necessary to restrict or constrain the flow or run-out of this encapsulating material so that it does not cover the BGA pads or other electric connections on the surface, thereby preventing electrical connections from being made in a subsequent manufacturing step, e.g., joining the chip carrier to the circuit board or card substrate.
One proposed solution to constrain or restrict the flow of the encapsulant material was to build a wall of material around the wire bond pads to separate the wire bond pads from the BGA pads so as to physically prevent the encapsulant from flowing if there was somewhat of an excess of encapsulant above and beyond what was needed to cover the chip, the wires and the wire bond pads. This has proved ineffective for two reasons. One principal reason is that the surface tension of the encapsulant material, together with the nature of the substrate of the chip carrier, allowed or indeed caused the encapsulant material to run over the wall and thereby defeat the purpose of the wall by allowing the encapsulant to reach electrical connections such as the BGA pads on the other side of the wall. Another reason, coupled with the surface tension of the encapsulant and the surface characteristics of the substrate, is that if a wall is physically constructed between the BGA pads and the wire bond pads, the sides of the wall tend to be sloping and thus promote the flow of the encapsulant material, thus enhancing the surface tension action.
Another proposal to restrict or constrain encapsulant material was to form a trench into the substrate surrounding the wire bond pads between the wire bond pads and the BGA pads so as to receive the encapsulant material. This also proved to have a disadvantage in that the surface tension of the encapsulant material often prevented it from entering into the trench. While this is effective to prevent the unintended outward flow, nevertheless it was not a satisfactory solution in many instances because the trench around the wire bond pads exposed subsurface wiring which was required to be covered, and if the encapsulant material did not enter the trench, it would leave this subsurface wiring exposed. Thus, both solutions, of a single wall or a trench, proved to be unsatisfactory to constraining or restricting the flow of encapsulant material while encapsulating an I/C chip wire bonded to wire bond pads on the dielectric substrate when BGA pads were located on the same side and in relatively close proximity to the I/C chip being bonded.